片间高速串行收发电路的低功耗技术研究
序号 | 标题 | 类型 | 作者 |
---|---|---|---|
1 | A low latency transceiver macro with robust design technique for processor interface | 会议论文 | Chiang, Patrick|Zongren, Yang|Feng, Zhang|Weiwu, Hu|Yi, Yang| |
2 | A novel SST transmitter with mutually decoupled impedance self-calibration and equalization | 会议论文 | Zhang, Feng|Chen, Shuai|Yang, Liqiong|Jing, Hua|Gao, Zhuo| |
3 | Sinusoidal clock sampling for multigigahertz ADCs | 期刊论文 | Chiang, Patrick|Hu, Weiwu|Xia, Lingli|Zhang, Feng|Yang, Zongren|Bai, Rui|Wang, Jingguang| |
4 | 基于电感电容振荡器的电荷泵锁相环的设计 | 期刊论文 | 张锋|袁莉|周玉梅| |
5 | A 10Gb/s wire-line transceiver with half rate period calibration CDR | 会议论文 | Chiang, Patrick|Yu, Hang|Gao, Zhuo|Yang, Yi|Zhang, Feng| |
6 | The implementation and design methodology of a quad-core version Godson-3 microprocessor | 会议论文 | Liang Yang|Feng Zhang |Zhuo Gao|Baoxia Fan|Ru Wang | |
7 | A high speed low jitter LVDS output driver for serial links | 期刊论文 | Zhou, Yumei|Ju, Hao|Wu, Bin|Zhang, Feng|Lv, Junsheng|Zhao, Jianzhong|Jiang, Jianhua|Yuan, Li| |
8 | A Low-Power High-Swing Voltage-Mode Transmitter | 期刊论文 | Shi Xiaobing| Yang Liqiong| Li Hao|ZhongShiqiang|Chen Shuai|YangZongren| |