| 1 |
层次式FPGA快速布局算法
|
期刊论文 |
戴晖|曾祥智|Bian Jinian|周强|Dai Hui|Zhou Qiang|边计年|Zeng Xiangzhi| |
| 2 |
层次式FPGA快速可布性布线算法
|
期刊论文 |
蔡懿慈|张星星|周强| |
| 3 |
预先指定单元位置的时延驱动布局优化方法
|
期刊论文 |
刘大为|边计年|Liu Dawei|Bian Jinian|周强|Zhou Qiang| |
| 4 |
SIAR: Splitting-graph-based interactive analog router
|
会议论文 |
Yao, Hailong|Cai, Yici|Zhou, Qiang|Yang, Fan| |
| 5 |
A nonlinear placement technique for FPGA-like uniform granularity problem
|
会议论文 |
Gao, Wenchao|Xin, Wu|Zhou, Qiang|Yan, Haixia|Qian, Xu|Lv, Yongqiang| |
| 6 |
应用于大规模FPGA的解析式布局算法
|
期刊论文 |
钱旭|吕勇强|周强|闫海霞|高文超| |
| 7 |
基于线性规划的最小扰动标准单元合法化算法
|
期刊论文 |
CHEN Fuzhen|闫海霞|YAN Haixia|L(U) Yongqiang|陈福真|吕勇强|周强|ZHOU Qiang| |
| 8 |
考虑重叠度和线长的单元密度平滑方法
|
期刊论文 |
周强|刘大为|边计年| |
| 9 |
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
|
会议论文 |
Cai, Y.|Zhou, Q.|Yao, H.|Niu, F.|Yang, J.|Sze, C.N.| |
| 10 |
Markov clustering based placement algorithm for island-style FPGAs
|
会议论文 |
Zhou, Qiang|Bian, Jinian|Dai, Hui|He, Ou| |
| 11 |
Cell Shifting Aware of Wirelength and Overlap
|
会议论文 |
Hong, Xianlong|Liu Dawei|Zhou, Qiang|Cai, Yici|Bian, Jinian| |
| 12 |
一种利用图建模的宏模块合法化算法
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期刊论文 |
周强|吴鑫|吕勇强|钱旭|刁屹|闫海霞| |
| 13 |
A fast routability-driven router for hierarchical FPGAs based on tabu search
|
会议论文 |
Cai, Yici|Zhang, Xingxing|Zhou, Qiang| |
| 14 |
Partition-based global placement considering wire-density uniformity for CMP variations
|
期刊论文 |
Dong, C.|Liu, D.|Zhou, Q.|Cai, Y.| |
| 15 |
Clock Tree Construction and Buffer Planning in Placement
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会议论文 |
Renwei Liu|Yici Cai|Weixiang Shen| |
| 16 |
An effective detailed placement algorithm for large-scale mix-mode IC design
|
会议论文 |
Yan, Haixia|Diao, Yi|Zhou, Qiang|Lv, Yongqiang| |
| 17 |
A thermal-driven force-directed floorplanning algorithm for 3D ICs 1
|
会议论文 |
Huang, Y.|Zhou, Q.|Cai, Y.|Yan, H.| |
| 18 |
A single layer zero skew clock routing in X architecture
|
期刊论文 |
Hong XianLong|Cai YiCi|Hu Jiang|Lu Bing|Shen WeiXiang| |
| 19 |
Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources
|
会议论文 |
Bian, Jinian|Zhou, Qiang|Yu, Junbo| |
| 20 |
Fast placement for large-scale hierarchical FPGAs
|
会议论文 |
Hong, Xianlong|Cai, Yici|Bian, Jinian|Dai, Hui|Zhou, Qiang| |
| 21 |
Useful clock skew optimization under a multi-corner multi-mode design framework
|
会议论文 |
Lu, Yongqiang|Hu, Jiang|Cai, Yici|Zhou, Qiang|Chen, Wei|Shen, Weixiang| |
| 22 |
针对宏模块的合法化技术
|
期刊论文 |
ZHOU Qiang|高文超|YAN Hai-xia|陈福真|钱旭|QIAN Xu|LU Yong-qiang|吕勇强|周强|GAO Wen-chao|闫海霞|CHEN Fu-zhen| |
| 23 |
Minimization of circuit delay and power through gate sizing and threshold voltage assignment
|
会议论文 |
Zhou, S.|Yao, H.|Cai, Y.|Zhou, Q.| |
| 24 |
基于FastPlace总体布局算法的实现
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期刊论文 |
周强|马小伟|闫海霞|钱旭|王似飞|吕勇强| |
| 25 |
Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation
|
期刊论文 |
Bian, Jinian|Yu, Junbo|Qu, Gang|Zhou, Qiang| |
| 26 |
Behavioral level dual-Vth design for reduced leakage power with thermal awareness
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会议论文 |
Bian, Jinian|Zhou, Qiang|Yu, Junbo|Qu, Gang| |
| 27 |
A fast rectangular spreading technique in global placement
|
会议论文 |
Ma, Xiaowei|Lv, Yongqiang|Yan, Haixia|Zhou, Qiang| |
| 28 |
A low power clock network placement framework
|
会议论文 |
Zhou, Qiang|Lv, Yongqiang|Bian, Jinian|Liu, Dawei| |
| 29 |
Fast congestion-aware timing-driven placement for Island FPGA
|
会议论文 |
Zhao, Jinpeng|Zhou, Qiang|Cai, Yici| |
| 30 |
Power optimization through edge reduction in LUT-based FPGA technology mapping
|
会议论文 |
Cai, Yici|Zhou, Qiang|Wei, Xing|Chen, Juanjuan| |
| 31 |
Efficient Hierarchical Algorithm for Mixed Mode Placement in Three Dimensional Integrated Circuit Chip Designs
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期刊论文 |
Yan, Haixia|Li, Zhuoyuan|Zhou, Qiang|Hong, Xianlong| |
| 32 |
A reliable detail placement tool for mixed mode IE design
|
会议论文 |
Lv, Yongqiang|Zhou, Qiang|Chen, Fuzhen|Yan, Haixia| |
| 33 |
Multilevel optimization for large-scale hierarchical FPGA placement
|
期刊论文 |
Bian, Ji-Nian|Zhou, Qiang|Dai, Hui| |
